The present invention relates generally to digital circuits, and more specifically, to clock gating cells used in digital circuits.
A clock signal is used in a digital circuit to synchronize the operation of various functional blocks of the digital circuit. A functional block may include a plurality of storage elements such as flip-flops or latches. A storage element changes its output based on a change in the levels of the clock signal that is received at a clock input of the storage element. However, during certain stages of the operation, storage elements in the functional blocks are not required to change their states based on the switching of the clock signal. Therefore, providing a continuous clock signal to the clock input of such storage elements results in power loss. The power loss is caused by the repetitive charging and discharging of the capacitive load associated with the clock input of the storage elements.
Therefore, in order to minimize power loss, clock signals are switched using additional logic circuitry to obtain gated clock signals. The gated clock signals switch states only when the logic states of the storage elements need to be changed. The additional logic circuitry is known as a clock gating cell.
Referring now to FIG. 1, a schematic diagram illustrating a conventional clock gating cell 100 is shown. The conventional clock gating cell 100 includes a negative latch 102, an input stage 104, a clock input stage 106, an output stage 108, and a logic AND gate 110. An input clock signal (CLK_IN) is provided to the clock input stage 106. An input signal (LAT_IN) is provided to the input stage 104. CLK_IN may periodically switch between a low state and a high state. When CLK_IN switches to a low state, LAT_IN gets latched at the output stage 108, i.e., an output signal (LAT_OUT) obtained from the output stage 108 becomes equal to LAT_IN. In contrast, when CLK_IN switches to high state, LAT_OUT remains in its previous state. Thereafter, LAT_OUT obtained from the output stage 108 and CLK_IN are provided to the input of the logic AND gate 110 to generate a gated clock signal (GATE_CLK).
Referring now to FIG. 2, a timing diagram illustrating an exemplary operation of the conventional clock gating cell 100 is shown. The timing diagram shows waveforms for an input clock signal (CLK_IN), an input signal (LAT_IN), an output signal (LAT_OUT), and a gated clock signal (GATE_CLK). At time t0, CLK_IN provided at the clock input stage 106 switches to high state. Subsequently, at time t1, LAT_IN provided at the input stage 104 becomes high. Since CLK_IN has switched to a high state, LAT_IN is not latched during the time between t1 and t2. GATE_CLK obtained at the output of the logic AND gate 110 remains low. At time t2, when CLK_IN switches to a low state, LAT_IN gets latched at the output stage 108, i.e., LAT_OUT obtained from the output stage 108 becomes equal to LAT_IN. Thereafter, at time t3, CLK_IN switches to a high state followed by GATE_CLK becoming high, since CLK_IN and LAT_OUT are provided at the input of the logic AND gate 110. Further, during the time between t3 and t4, GATE_CLK follows CLK_IN. Subsequently, at time t4, LAT_IN becomes low. Hence, LAT_IN is immediately latched at the output stage 108, i.e., LAT_OUT obtained from the output stage 108 becomes equal to LAT_IN. Consequently, LAT_OUT provided by the output stage 108 becomes low. The GATE_CLK thus generated switches only when LAT_OUT becomes high, thereby preventing power loss in the storage elements of the digital circuit.
However, in the conventional clock gating cell 100, CLK_IN continuously switches at the clock input stage 106 irrespective of whether LAT_IN is high or low. The continuous switching of CLK_IN causes continuous charging and discharging of the capacitive load associated with the clock input stage 106, thereby causing power loss in the conventional clock gating cell 100.